1. Field of the Invention
The present invention relates to DA converters applicable to solid-state imaging devices as represented by CMOS image sensors. The invention also concerns solid-state imaging devices, and camera systems.
2. Description of the Related Art
Generally, the current-controlled digital-analog converter (hereinafter, “DA converter (digital analog converter)”) is structured from a plurality of basic current supply cells that generates a constant current, and an output resistor provided as a current-voltage converter.
FIGS. 1A and 1B are schematic diagrams explaining basic structures of a current-controlled DA converter.
FIG. 1A represents a ground GND-based structure. FIG. 1B represents a structure based on power supply Vdd.
Basically, DA converters 1a and 1b are structured to include a base resistor R1, a counter CNT1, and a current supply I1 including a plurality of basic current supply cells.
In the ground-based DA converter 1a illustrated in FIG. 1A, the base resistor R1 is connected on the ground GND side, whereas the base resistor R1 is connected on the power supply Vdd side in the power supply-based DA converter 1b of FIG. 1B.
In the DA converters 1a and 1b, the input clock CLK to the counter CNT1 is counted, the number of selected basic current supply cells in the current supply is determined based on the counted value, and the resulting current is flown to the base resistor R1 to provide a ramp waveform for the voltage of the resistance value.
FIG. 2 is a circuit diagram illustrating a specific exemplary configuration of the ground-based DA converter (see, for example, JP-A-2007-59991 disclosing a DA converter, an AD converter, and a semiconductor device).
A ground-based DA converter 1a illustrated in FIG. 2 includes an analog signal output section 2, a gain control signal generating section 3, a counter decoder 4, and a gain decoder 5.
The analog signal output section 2 generates an analog signal according to a value of a digital input signal DI1 decoded in the counter decoder 4. The analog signal output section 2 adjusts the gain of the analog signal generated according to a bias voltage Vbias supplied as a gain control signal from the gain control signal generating section 3.
The analog signal output section 2 illustrated in FIG. 2 includes a plurality of basic current supply cells 2-1 to 2-n, each including a differential transistor, and a transistor provided as a current supply for the differential transistor. The basic current supply cells 2-1 to 2-n receive a common bias voltage through the gates of the current supply transistors.
In the ground-based DA converter 1a, the basic current supply cells 2-1 to 2-n are formed by p-channel MOS (PMOS) transistors.
The analog signal output section 2 includes a select output line LO1, a non-select output line NLO1, and an output resistor R2 that serves as a current-voltage converting circuit (IV converting circuit).
In the basic current supply cells 2-1 to 2-n, the drains of one of the transistors of the differential transistors are commonly connected to the select output line L01, and the drains of the other transistors are commonly connected to the non-select output line NLO1.
The select output line LO1 is connected to ground GND via the output resistor R2. The non-select output line NLO1 is directly connected to ground GND.
One of the transistors of the differential transistors in the basic current supply cells 2-1 to 2-n are selected according to the decode information from the counter decoder 4. In response, the current outputs of the selected basic current supply cells are added to produce an output current Iramp that flows into the select output line L01. The current Iramp is output after being converted to a voltage signal in the output resistor R2.
When the other transistors are selected in the basic current supply cells 2-1 to 2-n according to the decode information from the counter decoder 4, the current outputs of the selected basic current supply cells is added to produce a non-output current Iramp_minus that flows into ground GND via the non-select output line NLO1.
The gain control signal generating section 3 generates a bias voltage Vbias as a gain control signal that depends on the value of the digital gain control signal DGI1 decoded by the gain decoder 5.
The gain control signal generating section 3 illustrated in FIG. 2 includes a plurality of basic current supply cells 3-1 to 3-n, each including a differential transistor, and a current supply transistor for the differential transistor.
The basic current supply cells 3-1 to 3-n receive a bias voltage according to a common reference current through the gates of the current supply transistors.
In the ground-based DA converter 1a, the basic current supply cells 3-1 to 3-n are formed by n-channel MOS (NMOS) transistors.
The gain control signal generating section 3 includes a select line L1, a non-select line NL1, and a diode-connected PMOS transistor P3 that serves as an IV converting circuit.
The drains of one of the transistors of the differential transistors in the basic current supply cells 3-1 to 3-n are commonly connected to the select line L1, whereas the drains of the other transistors are commonly connected to the non-select line NL1.
The select line L1 is connected to the drain and gate of the PMOS transistor P3, and the connection node is connected to the gates of the current supply transistors of the basic current supply cells 2-1 to 2-n in the analog signal output section 2.
Specifically, a current mirror circuit is formed by the PMOS transistor P3 and the current supply transistors of the basic current supply cells 2-1 to 2-n. 
The non-select line NL1 is directly connected to the power supply Vdd.
One of the transistors of the differential transistors in the basic current supply cells 3-1 to 3-n are selected according to the decode information from the gain decoder 5.
In response, the current outputs of the selected basic current supply cells are added to produce a gain current Igain that flows into the select line L1. The gain current Igain is converted to a voltage signal in the PMOS transistor P3, and output to the analog signal output section 2.
When the other transistors are selected in the basic current supply cells 3-1 to 3-n according to the decode information from the gain decoder 5, the current outputs of the selected basic current supply cells are added to produce a non-select current Igain_minus that flows into the power supply Vdd via the non-select line NL1.
Such current-controlled DA converters are also used as analog-digital converters (hereinafter, “AD converter (analog digital converter)”) that perform the analog-digital conversion of the pixel signals in a solid-state imaging device (image sensor) that includes a matrix array of unit pixels.
Solid-state imaging devices including this type of AD converter are disclosed in, for example, JP-A-2007-59991 (DA converter, AD converter, semiconductor device), JP-A-2000-152082 (image sensor), and JP-A-2002-232291 (analog-digital converter, and image sensor using same).
In the solid-state imaging devices described in these publications, the analog pixel signals selected per line or per pixel are compared with a reference voltage (ramp waveform RAMP) that has been monotonously varied for analog to digital conversion, using a voltage comparator.
Concurrently with the comparison process, the solid-state imaging device performs a count process in a counter section, and acquires the digital signal of the pixel signal based on the counted value at the completion of the comparison process.